A. The Field of the Invention
The embodiments of the present invention relate to a scan configuration, and more particularly, the embodiments of the present invention relate to a scan-load-based dynamic scan configuration.
B. The Description of the Prior Art
Various scan design methodologies1 have been successfully used in digital systems and credited with improved testability, reduced cost of test and diagnosis, reduced time for process and system debugging, better system maintenance and serviceability, etc., among many manufacturing-critical and system develop metrics.2 Scan structures provide access points for controllability and observability to internal circuits, and are also essential to many test and test data compression techniques, such as STUMPS,3 the Illinois Scan Architecture,4 and SmartBIST,5 and many other well-known scan methods.6 Scan structures are typically customized on silicon for individual designs. With these techniques, scan configurations—once the circuit structures are placed on silicon—cannot be changed in post-silicon processes, such as test, diagnosis, and debug, limiting the space for optimal efficiency and effectiveness of these applications. 1 E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testing,” in the Proceedings of the 14th Design Automation Conference, pp. 462-468, June, 1977; E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for LSI Testability,” Journal of Design Automation & Fault-Tolerance Computing, Vol. 2, No. 2, pp. 165-178, May, 1978; E. B. Eichelberger, T. W. Williams, E. I. Muehldorf, and R. G. Walther, “A Logic Design Structure for Testing Internal Array,” in the Proceedings of the 3rd USA-JAPAN Computer Conference, pp. 266-272, October, 1978; A. Kobayashi, S. Matsue and H. Shiba, “Flipflop Circuit with FLT (Fault-Location-Technique) Capability,” (in Japanese) in the Proceedings of IECEO Conference, pp. 962, 1968; Y. Miyagi, A. Kobayashi, and K. Kitano, “Hardware System of NEAC Series 2200 Model 700,” (in Japanese) Paper Technology Group, IECE, Japan, TGOEC71-3, April 1971.2 S. DasGupta, R. G. Walther, and T. W. Williams, “An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceability,” in the Digest of Papers of the 11th Annual International Symposium on Fault-Tolerant Computing, pp. 32-34, June 1981; W. C. Carter, H. C. Montgomery, R. J. Presis and H. J. Reinheimer, “Design of Serviceability Features for the IBM System/360,” IBM Journal of Research & Development, pp. 115-126, 1964; K. Maling and E. L. Allen, “A Computer Organization and Programming System for Automated Maintenance,” IEEET-EC: 63, pp. 887-895; J. H. Stewart, “Application of Scan/Set for Error Detection and Diagnostics,” in the Digest of Papers of Semiconductor Test Conference, pp. 152-158, 1978.3 P. H. Bardell and W. H. McAnney, “Self-Testing of Multiple Logic Modules,” in the Digest of Papers of International Test Conference, pp. 200-204, November 1982; P. H. Bardell and W. H. McAnney, “Parallel Pseudorandom Sequences for Built-in Test,” in the Proceedings of International Test Conference, pp. 302-308, October 1984; P. H. Bardell and W. H. McAnney, “Simultaneous Self-Testing System,” U.S. Pat. No. 4,513,418, Apr. 23, 1985.4 I. Hamzaoglu and J. H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” in the Proceedings of IEEE International Symposium on Fault Tolerant Computing, 1999, pp. 260-267; I. Hamzaoglu and J. H. Patel, “Reducing Test Application Time for Built-in Self-Test Test Pattern Generators,” in the Proceedings of IEEE VLSI Test Symposium, pp. 369-375, 2000.5 B. Koenemann et al., “Logic DFT and Test Resource Partitioning for 100M Gate ASICs,” presentation at the Test Resource Partitioning Workshop (TRP), 2000; B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, “A SmartBIST Variant with Guaranteed Encoding,” in the Proceedings of the 10th Asian Test Symposium, pp. 325-332, 2001.6 M. S. Abadir and M. A. Breuer, “Scan Path with Look Ahead Shifting,” in the Proceedings of International Test Conference, pp. 165-170, June, 1985; M. S. Abadir, “Efficient Scan Path Testing Using Sliding Parity Response Compaction,” in the Proceedings of International Conference on Computer Aided Design, pp. 332-335, November, 1987; K. T. Cheng and V. D. Agrawal, “An Economical Scan Design for Sequential Logic Test Generation,” in the Proceedings of 19th International Symposium on Fault-Tolerant Computing, pp. 28-35, June 1989; S. DasGupta, P. Goel, R. G. Walther, and T. W. Williams, “A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI,” in the Proceedings of International Test Conference, pp. 63-66, November 1982; S. P. Morley and R. A. Malett, “Selectable Length Partial Scan: A Method to Reduce Vector Length,” in the Proceedings of the International Test Conference, pp. 385-392, 1991; C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, “OPMISR: The Foundation for Compressed ATPG Vectors,” in the Proceedings of the International Test Conference, pp. 748-757, October 2001; C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, A. Ferko, B. Keller, D. Scott, B. Koenemann, and T. Onodera, “Extending OPMISR beyond 10× Scan Test Efficiency,” IEEE Design & Test of Computers, pp. 65-72, Vol. 19, No. 5, September/October 2002.
Dynamically reconfigurable scan chains7 can effectively reduce the cost of test. With dynamic scan, a MUX is placed at the output of a scan cell. When selected, the MUX can direct the scan-in to by-pass the scan cell. To reduce the use of the MUX blocks, a MUX may be used to by-pass a segment of a scan chain. Dynamic scan can also be applied to parallel scan chains. Random access scan (RAS) methods8 reduce test time and power consumption, as well as overcoming many other disadvantages associated with the classic serial scan, by enabling each scan cell to be uniquely and randomly addressable. The outputs of selected scan cells can also be directed to primary outputs for observation. These methods use large amount of interconnect resources to distribute many configuration or decoded address signals. Other MUX-based scan configuration techniques, such as the CircularScan9 and Virtual Scan Chains,10 have also been described to reduce test cost. 7 S. Narayanan and M. Breuer, “Optimal Configuring of Multiple Scan Chains,” IEEE Transactions on Computers, Vol. 42, No. 9, pp. 1121-1131, September 1993; S. Narayanan and M. Breuer, “Reconfiguration Techniques for a Single Scan Chain,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 6, pp. 750-765, 1995; A. R. Pandey and J. H. Patel, “Reconfiguration Techniques for Reducing Test Time and Test Data Volume in Illinois Scan Structure Based Designs,” in the Proceedings of IEEE VLSI Test Symposium, pp. 9-15, 2002; S. Samaranayake, N. Sitchinava, R. Kapur, M. B. Amin, and T. W. Williams, “Dynamic Scan: Driving Down the Cost of Test,” IEEE Computer, pp. 63-68, October 2002; S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, M. B. Amin, and T. W. Williams, “A Reconfigurable Shared Scan-in Architecture,” in the Proceedings of IEEE VLSI Test Symposium, 00. 9-14, 2003.8 H. Ando, “Testing VLSI with Random Access Scan,” in the Proceedings of the COMPCON, pp. 50-52, February 1980; K. D. Wagner, “Design for Testability in the AMDAHL 580,” in the Proceedings of the COMPCON, pp. 384-388, 1983; D. H. Baik, K. K. Saluja, and S. Kajihara, “Random Access Scan: A Solution to Test Power, Test Data Volume and Test Time,” in the Proceedings of the 17th International Conference on VLSI Design, pp. 883-888, January 2004; A. S. Mudlapur, V. D. Agrawal and A. D. Singh, “A Random Access Scan Architecture to Reduce Hardware Overhead,” in the Proceedings of International Test Conference, Paper 15.1, November 2005.9 B. Arslan and A. Orailoglu, “Test Cost Reducation through a Reconfigurable Scan Architecture,” in the Proceedings of the International Test Conference, pp. 945-952, October 2004; B. Arslan and A. Orailoglu, “CircularScan: A Scan Architecture for Test Cost Reduction,” in the Proceedings of the Design Automation and Test in Europe Conference and Exhibition, pp. 1290-1295, 2004.10 A. Jas, B. Pouya and N. A. Touba, “Virtual Scan Chains: A Means for Reducing Scan Length in Cores,” in the Proceedings of the IEEE VLSI Test Symposium, pp. 73-78, April 2000.
Pre-structured, such as standard-cell, and pre-manufactured, such as FPGA, platforms, have been the main implementation vehicles for ASIC designs. Integration of design-for-test (DFT) circuit structures, such as scan circuits, is often executed based on individual designs, requiring DFT engineer(s) to insert and configure scan structures into each design. As large designs often contain more than 250 k scan cells, this DFT effort adds additional design development time and sometimes interferes with timing and other design issues, such as interconnect routing contention. It is important to point out that, with current practices, manufacturing test related circuitry is implemented as part of a design and during the design development process.
It is desirable to share a large number of manufacturing masks between individual ASIC designs. This is not only to reduce manufacturing cost, but also to maintain the quality and predictability of manufacturing process. Therefore, it seems to make every sense to embed all manufacturing test related circuit structures in implementation platforms, so that scan configuration is no longer a design issue and masks containing manufacturing test circuitry are fixed in each platform. This requires a scan-load-based dynamic scan configuration that reconfigures scan structures via scan-load operation, to thereby eliminate interconnect network distributing configuration signals that can be later reconfigured for individual designs in after-silicon applications, such as test, diagnosis and design debug. The above mentioned various MUX-based dynamic scan methods are not good candidates for this scan-load-based dynamic scan configuration that reconfigures scan structures via scan-load operation, to thereby eliminate interconnect network distributing configuration signals because more or less these methods use interconnect, and hence additional routing space, to distribute configuration signals.
Thus, there exists a need for a scan-load-based dynamic scan configuration that reconfigures scan structures via scan-load operation, to thereby eliminate interconnect network distributing configuration signals having minimum hardware and reconfiguration operation overhead.
Some of the concerns with the above mentioned MUX-based approaches are centered with the use of potentially large interconnect network to distribute dynamic configuration signals to each and every scan cells or segments. This direct-control via PIs provides the most flexibility to reconfigure and/or manipulate scan data, with the cost of using considerable interconnect routing space. Other concerns are related to signal integrity that may be affected by the distribution network which is likely to contain many long interconnects.
On the other hand, scan-load (a.k.a. scan-in) operation is used to shift data into scan cells. Therefore, it can be used to distribute reconfiguration signals to the scan cells. This would eliminate the distribution network used by MUX-based methods. To use scan-load operation to distribute reconfiguration signals reconfigurable scan cells or segments must be able to hold configuration data and maintain the reconfigured scan configuration for normal scan load and unload (a.k.a. scan-out) operations. This hold function can be implemented by integrating existing scan cell designs with a small hold block.
The following three United States Patents were cited in the International Search Report of applicant's corresponding PCT International Patent Application number PCT/US2007/016088:
(1) The U.S. Pat. No. 4,493,077 to Agrawal et al.
The U.S. Pat. No. 4,493,077 issued to Agrawal et al. on Jan. 8, 1985 in U.S. class 714 and subclass 731 teaches a large scale sequential integrated circuit made amenable to scan design testing by inclusion of special multiplexing and storage circuits that respond to a pair of test control pulses to reconfigure the circuit to include one or more shift registers and to step the scan test data through the shift registers. In particular, the pair of test control pulses are applied to the two terminals to which, in normal operation, are applied to the clock pulses that are used to control the storage elements and which, in this operation, are never both simultaneously high. To initiate the scan test operation, these test control pulses are made simultaneously high and the circuitry responds to the conditions.
(2) The U.S. Pat. No. 6,265,894 to Reblewski et al.
The U.S. Pat. No. 6,265,894 issued to Reblewski et al. on Jul. 24, 2001 in U.S. class 326 and subclasss 39 teaches an integrated circuit including a plurality of logic elements (LEs), each of which having a plurality of outputs, and a partial scan register. The plurality of LEs are operative to generate a plurality of output signals in response to a plurality of input signals correspondingly applied to the LEs. The partial scan register is reconfigurably coupled to select ones of the LEs so that, when enabled, the partial scan register is operative to capture and output on a scan bus a record of signal state values circuit elements emulated by the selected LEs in a particular clock cycle of an operating clock. The partial scan register is enabled with application of a scan clock appropriately scaled to the operating clock.
(3) The U.S. Pat. No. 7,191,373 to Wang et al.
The U.S. Pat. No. 7,191,373 issued to Wang et al. on Mar. 13, 2007 in U.S. class 714 and subclass 729 teaches a method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, which includes scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. A DFD controller is used for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.